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    首頁(yè)產(chǎn)品索引MC100ELT23

    MC100ELT23

    購(gòu)買收藏
    ?Translator, Dual Differential PECL to TTL

    制造商:ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC100ELT23 is a dual differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the dual gate design of the ELT23 makes it ideal for applications which require the translation of a clock and a data signal.
    The PECL inputs are differential; therefore, the MC100ELT23 can accept any standard differential PECL input referenced from a V
    of 5.0 V.
    • 3.5ns Typical Propagation Delay
    • 24mA TTL Outputs
    • Flow Through Pinouts
    • ESD Protection: > 2 KV HBM, > 400 V MM
    • The 100 Series Contains Temperature Compensation
    • Operating Range V
    • = 4.75 V to 5.25 V with GND= 0 V
    • Internal Input Pulldown Resistors
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 91 devices
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC100ELT23DTR2GON 立即購(gòu)買
    MC100ELT23DR2GON 立即購(gòu)買
    MC100ELT23DGON 立即購(gòu)買
    MC100ELT23DTGON 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B)下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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