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    首頁產(chǎn)品索引MC100LVEL51

    MC100LVEL51

    購買收藏
    ?ECL Differential Clock D Flip-Flop

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3V supply. With propagation delays and output transition times essentially equal to the EL51, the LVEL51 is ideally suited for those applications which require the ultimate in AC performance at 3.3V V
    .
    The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the LVEL51 allow the device to be used as a negative edge triggered flip-flop.
    The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V
    and the CLKbar input will be biased at V
    /2.
    • 475ps Propagation Delay
    • 2.8GHz Toggle Frequency
    • ESD Protection: >4 KV HBM, >200 V MM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 114 devices
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100LVEL51MNR4GONIC FF D-TYPE SNGL 1BIT 8DFN 立即購買
    MC100LVEL51DTR2GONMC100LVEL51 是一款具有重置功能的差分時鐘 D 類觸發(fā)器。此器件功能與 EL51 器件相當(dāng)，但由 3.3V 電源供電。LVEL51 的傳播延遲和輸出轉(zhuǎn)換時間與 EL51 基本相當(dāng)，非常適合那些要求在 3.3V VCC 下具有最高交流性能的應(yīng)用。重置輸入為異步、電平觸發(fā)的信號。當(dāng)時鐘為低電平時數(shù)據(jù)進(jìn)入觸發(fā)器的主部分，然后傳輸?shù)綇牟糠?，并因此在時鐘發(fā)生正向轉(zhuǎn)換時傳輸?shù)捷敵?。LVEL51 的差分時鐘輸入支持將器件用作下降沿觸發(fā)的觸發(fā)器。該差分輸入采用箝位電路，以在開路輸入條件下保持穩(wěn)定性。保持開路時，CLK 輸入將下拉至 VEE，并且 CLKbar 輸入將在 VCC/2 處偏置。 立即購買
    MC100LVEL51DR2GONIC FF D-TYPE SNGL 1BIT 8SOIC 立即購買
    MC100LVEL51DGONIC FF D-TYPE SNGL 1BIT 8SOIC 立即購買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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