free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶:為給您持續(xù)提供一對(duì)一優(yōu)質(zhì)服務(wù),即日起,元器件訂單實(shí)付商品金額<300元時(shí),該筆訂單按2元/SKU加收服務(wù)費(fèi),感謝您的關(guān)注與支持!
    首頁(yè)產(chǎn)品索引MC10EP105

    MC10EP105

    購(gòu)買收藏
    ?3.3 V / 5.0 V ECL Quad 2-Input Differential AND/NAND Gate

    制造商:ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10/100EP105 is a quad 2-input differential AND/NAND gate. Each gate is functionally equivalent to the EP05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP105 is ideal for applications requiring the fastest AC performance available.
    The 100 Series contains temperature compensation.
    • 275ps Typical Propagation Delay
    • Maximum Frequency > 3 Ghz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10EP105FAGON 立即購(gòu)買
    MC10EP105FAR2GONIC AND/NAND QUAD 2INP ECL 32LQFP 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B)下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    MC10E457MIS2DHMIC5011MCP14A0451
    MIC4422AMC14029BMCP48FVB01MC33272A
    MM1Z6V8MC10EP01MC10E116MC100EL1648
    MIC2128MCP6441MIC3263MCP621
    MC33363BMIC2164MCP6G01MC74HCT259A
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號(hào)工商網(wǎng)監(jiān)認(rèn)證 工商網(wǎng)監(jiān) 營(yíng)業(yè)執(zhí)照