優(yōu)勢(shì)和特點(diǎn)

  Low phase noise, phase-locked loop (PLL) (Please see data sheet for additional details.)

  Twelve 800 MHz LVDS outputs divided into 4 groups (Please see data sheet for additional details.)

  Automatic synchronization of all outputs on power-up

  Manual synchronization of outputs as needed

  SPI- and I2C-compatible serial control port

  64-lead LFCSP

  Nonvolatile EEPROM stores configuration settings

產(chǎn)品詳情

The AD9522-51 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.???

The AD9522 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.

The AD9522 features 12 LVDS outputs in four groups. Any of the 800 MHz LVDS outputs can be reconfigured as two 250 MHz CMOS outputs.

Each group of outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase (coarse delay) to be set.

The AD9522 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage up to 5.5 V.

The AD9522 is specified for operation over the standard industrial range of ?40°C to +85°C.

The AD9520-5 is an equivalent part to the AD9522-5 featuring LVPECL/CMOS drivers instead of LVDS/CMOS drivers.

1The AD9522 is used throughout this data sheet to refer to all the members of the AD9522 family. However, when AD9522-5 is used, it is referring to that specific member of the AD9522 family.

Applications

  Low jitter, low phase noise clock distribution

  Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols

  Forward error correction (G.710)

  Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

  High performance wireless transceivers

  ATE and high performance instrumentation

  Broadband infrastructures