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    首頁產(chǎn)品索引MC10EP445

    MC10EP445

    購買收藏
    ?3.3 V / 5.0 V ECL 8-Bit Serial to Parallel Converter

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10/100EP445 is an integrated 8-bit differential serial to parallel data converter with frame asynchronous data resynchronization. The device is designed to operate for NRZ data rates of up to 5.0 Gb/s. The conversion sequence was chosen to convert the first serial bit to Q0, the second bit to Q1, etc. Two selectable differential serial inputs, which are selected by SINSEL, provide this device with loop-back testing capability. The MC10/100EP445 has a Sync pin which, when held high for at least two consecutive clock cycles, will swallow one bit of data shifting the start of the conversion data from D
    to D
    . Each additional shift requires an additional pulse to be applied to the Sync pin.
    Extra control pins are provided to reset and disable internal clock circuitry. Additionally, V
    pin is provided for single-ended input condition.
    The 100 Series contains temperature compensation.
    • 1530 ps Propagation Delay
    • 5.0 Gb/s Data Rate Capability
    • Differential Clock and Serial Inputs
    • V
    • Output for Single-Ended Input Applications
    • Asynchronous Data Synchronization (SYNC)
    • Asynchronous Master Reset (RESET)
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • =-3.0 V to -5.5 V
    • Open Input Default State
    • CLK ENABLE Immune to Runt Pulse Generation
    • Pb-Free Packages are Available

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    在線購買

    型號制造商描述購買
    MC10EP445FAGONData Management Interface 32-LQFP (7x7) 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載

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