free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶(hù):為給您持續(xù)提供一對(duì)一優(yōu)質(zhì)服務(wù),即日起,元器件訂單實(shí)付商品金額<300元時(shí),該筆訂單按2元/SKU加收服務(wù)費(fèi),感謝您的關(guān)注與支持!
    首頁(yè)產(chǎn)品索引MD1812

    MD1812

    購(gòu)買(mǎi)收藏
    HIGH SPEED QUAD MOSFET DRIVER

     

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    MD1812 is a high-speed quad MOSFET driver. It is designed to drive two N and two P-channel high voltage DMOS FETs for medical ultrasound applications, but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD1812 is a high-speed level translator that is able to operate from logic input signals of 1.8 to 5.0V amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic 1 levels. The level translator uses a proprietary circuit which provides DC coupling together with high-speed operation. The output stage of the MD1812 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages.As an example, the input logic levels may be 0V and 1.8V, the control logic may be powered by +5V and –5V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0 amps depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A and C outputs high and the B and D outputs low. This assists in properly pre-charging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A built-in level shifter provides PMOS gate negative bias drive. This enables the user-defined damping control to generate return-to-zero bipolar output pulses.

      6.0ns rise and fall time

      2.0A peak output source/sink current

      1.8 to 5.0V input CMOS compatible

      Smart logic threshold

      Low jitter design

      Quad matched channels

      Drives two N and two P-channel MOSFETs

      Outputs can swing below ground

      Built-in level translator for negative gate bias

      User-defined damping for return-to-zero application

      Low inductance quad flat no-lead package

      Thermally-enhanced package

    電路圖、引腳圖和封裝圖

    在線購(gòu)買(mǎi)

    型號(hào)制造商描述購(gòu)買(mǎi)
    MD1812K6-GATSHEATSINK25X25X15MML-TABT412 立即購(gòu)買(mǎi)

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    MC10EP33MMBTA28MJ11022MC74HCT573A
    MSP430FR2533MC74VHC1G86MC100LVEP16MMBF4118
    MOC3063MMC100EP57MCP6S93MC74VHC1GT02
    MIC59P50MC100LVEL31MC74VHC1G14MCP2030
    MIC2774MIC24045MC74AC652MC74VHCT574A
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號(hào)工商網(wǎng)監(jiān)認(rèn)證 工商網(wǎng)監(jiān) 營(yíng)業(yè)執(zhí)照