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    首頁產(chǎn)品索引MC100LVEP14

    MC100LVEP14

    購買收藏
    5 Differential ECL/PECL/HSTL Clock / Data Fanout Buffer

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVEP14 is a low skew 1 to 5 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The ECL/PECL input signals can be either differential or single-ended (if the VBB output is used). HSTL inputs can be used when the LVEP14 is operating under PECL conditions.
    • 100 ps Device-to-Device Skew
    • 25 ps Within Device Skew
    • 400 ps Typical Propagation Delay
    • Maximum Frequency > 2 GHz Typical
    • PECL and HSTL Mode: V
    • = 2.375 V to 3.8 V with V
    • = 0 V
    • NECL Mode: V
    • = 0 V with V
    • = -2.375 V to -3.8 V
    • LVDS Input Compatible
    • Open Input Default State

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    在線購買

    型號制造商描述購買
    MC100LVEP14DTR2GONIC CLK BUFFER 2:5 2.5GHZ 20TSSOP 立即購買
    MC100LVEP14DTGONIC CLK BUFFER 2:5 2.5GHZ 20TSSOP 立即購買

    技術(shù)資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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