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    首頁產(chǎn)品索引MC100EP446

    MC100EP446

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    ?Serial to Parallel Converter, 3.3 V / 5 V, 8-Bit, CMOS / ECL / TTL Data Input

    制造商:ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10/100EP446 is an integrated 8-bit parallel to serial data converter. The device is designed with unique circuit topology to operate for NRZ data rates up to 3.2 Gb/s. The conversion sequence from parallel data into a serial data stream is from bit D0 to D7. The parallel input pins D0-D7 are configurable to be threshold controlled by CMOS, ECL, or TTL level signals. The serial data rate output can be selected at internal clock data rate or twice the internal data rate using the CKSEL pin.
    Control pins are provided to reset (SYNC) and disable internal clock circuitry (CKEN). In either CKSEL modes, the internal flip-flops are triggered on the rising edge for CLK and the multiplexers are switched on the falling edge of CLK, therefore, all associated specification limits are referenced to the negative edge of the clock input. Additionally, V
    pin is provided for single-ended input condition.
    The 100 Series devices contain temperature compensation network.
    • 3.2 Gb/s Typical Data Rate Capability
    • Differential Clock and Serial Inputs
    • V
    • Output for Single-ended Input Applications
    • Asynchronous Data Reset (SYNC)
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Parallel Interface Can Support PECL, TTL and CMOS
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100EP446MNGON 立即購買
    MC100EP446FAGONMC10/100EP446 是一款集成式 8 位并行至串行數(shù)據(jù)轉換器。該器件采用獨特的電路技術,可在高達 3.2 Gb/s 的 NRZ 數(shù)據(jù)速率下運行。從并行數(shù)據(jù)到串行數(shù)據(jù)流的轉換順序是從 D0 到 D7 位。并行輸入引腳 D0-D7 可配置為由 CMOS、ECL 或 TTL 電平信號控制的閾值??墒褂?CKSEL 引腳,以內(nèi)部時鐘數(shù)據(jù)速率或內(nèi)部數(shù)據(jù)速率的兩倍選擇串行數(shù)據(jù)速率輸出。提供控制引腳,用于重置 (SYNC) 和禁用內(nèi)部時鐘電路 (CKEN)。在任何一種 CKSEL 模式下,內(nèi)部觸發(fā)器在 CLK 的上升沿觸發(fā),而多路復用器在 CLK 的下降沿觸發(fā),因此,所有相關的規(guī)格限制都以時鐘輸入的負沿為參考。此外,還提供 VBB 引腳,用于單端輸入的情況。100 系列器件包含溫度補償網(wǎng)絡。 立即購買

    技術資料

    標題類型大小(KB)下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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