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    首頁(yè)產(chǎn)品索引MC100ELT28

    MC100ELT28

    購(gòu)買(mǎi)收藏
    ?Translator, TTL to Differential PECL and Differential PECL to TTL

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10ELT/100ELT28 is a differential PECL to TTL translator and a TTL to differential PECL translator in a single package. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the dual translation design of the ELT28 makes it ideal for applications which are sending and receiving signals across a backplane.
    The 100 Series contains temperature compensation.
    • 3.5ns Typical PECL to TTL Propagation Delay
    • 1.2ns Typical TTL to PECL Propagation Delay
    • PNP TTL Inputs for Minimal Loading
    • 24mA TTL Outputs
    • Flow Through Pinouts
    • ESD Protection: > 2 KV HBM
    • Operating Range V
    • = 4.75 V to 5.25 V with GND= 0 V
    • Q
    • Output Will Default High with Inputs Left Open or
    • Q
    • Output Will Default High with Inputs Left Open
    • Internal PECL Input Pulldown Resistors
    • Internal PECL Input Pulldown Resistors
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 71 devices
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購(gòu)買(mǎi)

    型號(hào)制造商描述購(gòu)買(mǎi)
    MC100ELT28DTGONIC XLATOR TTLPECL-PECLTTL 8TSSOP 立即購(gòu)買(mǎi)
    MC100ELT28DR2GONIC XLATOR PECL TTL 5V 8-SOIC 立即購(gòu)買(mǎi)
    MC100ELT28DGONIC TRNSLTR TTLPECL/PECLTTL 8SOIC 立即購(gòu)買(mǎi)

    技術(shù)資料

    標(biāo)題類(lèi)型大?。↘B）下載
    MC10ELT28_BD.GIFUNKNOW4 點(diǎn)擊下載
    MC10ELT28_PKG.GIFUNKNOW11 點(diǎn)擊下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載

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