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    首頁產(chǎn)品索引MC100LVEL30

    MC100LVEL30

    購買收藏
    ?ECL Triple D-Type Flip-Flop with Set and Reset

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVEL30 is a triple master-slave D flip flop with differential outputs. The MC100EL30 is pin and functionally equivalent to the MC100LVEL30 but is specified for operation at the standard 100E ECL voltage supply. Data enters the master latch when the clock input is LOW and transfers to the slave upon a positive transition on the clock input.
    In addition to a common Set input individual Reset inputs are provided for each flip flop. Both the Set and Reset inputs function asynchronous and overriding with respect to the clock inputs.
    • 1200MHz Minimum Toggle Frequency
    • 450 ps Typical Propagation Delays
    • ESD Protection: >2 KV HBM
    • The 100 Series Contains Temperature Compensation.
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: U-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 347 devices
    • Pb-Free Packages are Available

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    型號制造商描述購買
    MC100LVEL30DWGONIC FF D-TYPE TRPL 1BIT 20SOIC 立即購買
    MC100LVEL30DWR2GON 立即購買

    技術(shù)資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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