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    首頁(yè)產(chǎn)品索引MC10H135

    MC10H135

    購(gòu)買收藏
    ?DualMaster-Slave JK Flip-Flop

    制造商:ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10H135 is a dual JK master-slave flip-flop. The device is provided with an asynchronous set(s) and reset(R). These set and reset inputs overide the clock.
    A common clock is provided with separate Jbar-Kbar inputs. When the clock is static, the JK bar inputs do not effect the output. The output states of the flip flop change on the positive transition of the clock.
    • Propagation delay, 1.5 ns Typical
    • Power Dissipation, 280 mW mV Typical/Pkg. (No Load)
    • f
    • 250 MHz Max
    • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
    • Voltage Compensated
    • MECL 10K Compatible
    • Pb-Free Packages are Available

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10H135FNR2GONIC FF JK TYPE DUAL 1BIT 20PLCC 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大小(KB)下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載

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