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    首頁產(chǎn)品索引MC10E141

    MC10E141

    購買收藏
    ?ECL 8-Bit Shift Register

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10E/100E141 is an 8-bit full-function shift register. The E141 performs serial/parallel in and serial/parallel out, shifting in either direction. The eight inputs D
    -D
    accept parallel input data, while DL/DR accept serial input data for left/right shifting. The Qn outputs do not need to be terminated for the shift operation to function. To minimize noise and power, any Q output not used should be left unterminated.
    The select pins, SEL0 and SEL1, select one of four modes of operation: Load, Hold, Shift Left, Shift Right, according to the Function Table.
    Input data is accepted a set-up time before the positive clock edge. A HIGH on the Master Reset (MR) pin asynchronously resets all the registers to zero.
    The 100 Series contains temperature compensation.
    • 700MHz Min. Shift Frequency
    • 8-Bit
    • Full-Function, Bi-Directional
    • Asynchronous Master Reset
    • Pin-Compatible with E241
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • 75k
    • Input Pulldown Resistors
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • ESD Protection: > 2 kV HBM, > 200 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 565 devices
    • Pb-Free Packages are Available

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    型號制造商描述購買
    MC10E141FNGONIC SHIFT REGISTR 8BIT ECL 28PLCC 立即購買
    MC10E141FNR2GONIC SHIFT REGISTER 8BIT 28-PLCC 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載
    Interfacing with ECLinPSPDF72 點擊下載

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