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    首頁產(chǎn)品索引MC100EP196

    MC100EP196

    購買收藏
    ?3.3 V ECL Programmable Delay Chip

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100EP196 is a programmable delay chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides programmably variable delay of a differential ECL input signal. It has similar architecture to the EP195 with the added feature of further tuneability in delay using the FTUNE pin. The FTUNE input takes an analog voltage from V
    to V
    to fine tune the output delay from 0 to 60 ps.
    • Maximum Frequency > 1.2 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.6 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.6 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • A Logic High on the ENbar Pin Will Force Q to Logic Low
    • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
    • V
    • Output Reference Voltage
    • Pb-Free Packages are Available

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    在線購買

    型號制造商描述購買
    MC100EP196FAR2GONIC DELAY LN 1024TAP PROG 32LQFP 立即購買
    MC100EP196FAGONDelay Line IC Programmable 1024 Tap 2.36ns ~ 12.258ns 32-LQFP 立即購買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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