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    首頁(yè)產(chǎn)品索引NB7L32M

    NB7L32M

    購(gòu)買收藏
    ?÷·2 Divider with CML Output

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NB7L32M is an integrated /2 divider with differential clock inputs and asynchronous reset.
    Differential clock inputs incorporate internal 50 Ω termination resistors and accept LVPECL (Positive ECL), CML, or LVDS. The high frequency reset pin is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple NB7L32M's in a system.
    The differential 16 mA CML output provides matching internal 50 Ω termination which guarantees 400 mV output swing when externally receiver terminated 50 Ω to VCC (See Figure 16).
    The device is housed in a small 3x3 mm 16 pin QFN package.
    • Maximum Input Clock Frequency 14 GHz Typical
    • 200 ps Max Propagation Delay
    • 30 ps Typical Rise and Fall Times
    • Operating Range: V
    • = 2.375 V to 3.465 V with V
    • = 0 V
    • CML Output Level (400 mV Peak-to-Peak Output), Differential Output Only
    • 50 Ω Internal Input and Output Termination Resistors
    • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and SG Devices
    • Full RoHS Compliance.

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    NB7L32MMNGONIC CLOCK DIVIDER 1:2 16-QFN 立即購(gòu)買
    NB7L32MMNR2GONLOW SKEW CLOCK DRIVER 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Clock Generation and Clock and Data Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)PDF40 點(diǎn)擊下載
    GigaComm (SiGe) SPICE Modeling KitPDF157 點(diǎn)擊下載
    2.5V/3.3V, 14GHz ÷2 Clock Divider w/CML Output and Internal TerminationPDF183 點(diǎn)擊下載
    IBIS Model for NB7L32MUNKNOW24 點(diǎn)擊下載
    QFN16, 3x3, 0.5PPDF55 點(diǎn)擊下載

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