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    首頁產(chǎn)品索引MC100EP51

    MC100EP51

    購買收藏
    ?ECL D Flip-Flop with Reset and Differential Clock

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10/100EP51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 and LVEL51 devices.
    The reset input is an asynchronous, level triggered signal. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP51 allow the device to be used as a negative edge triggered flip-flop.
    The differential input employs clamp circuitry to maintain stability under open input conditions. When left open, the CLK input will be pulled down to V
    and the CLKbar input will be biased at V
    / 2.
    • 350ps Typical Propagation Delay
    • Maximum Frequency > 3 Ghz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Pb-Free Packages are Available

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    型號制造商描述購買
    MC100EP51MNR4GONIC FF D-TYPE SNGL 1BIT 8DFN 立即購買
    MC100EP51DTR2GONMC10/100EP51 是一款具有重置功能的差分時鐘 D 類觸發(fā)器。該器件的功能與 EL51 和 LVEL51 器件相同。重置輸入為異步、電平觸發(fā)的信號。當時鐘為低電平時數(shù)據(jù)進入觸發(fā)器的主部分，然后傳輸?shù)綇牟糠?，并因此在時鐘發(fā)生正向轉(zhuǎn)換時傳輸?shù)捷敵觥P51 的差分時鐘輸入允許該器件用作下降沿觸發(fā)的觸發(fā)器。差分輸入采用箝位電路來保持開路輸入條件下的穩(wěn)定性。保持開路時，CLK 輸入將下拉至 VEE，CLKbar 輸入將在 VCC / 2 處偏置。 立即購買
    MC100EP51DR2GON 立即購買
    MC100EP51DGON 立即購買
    MC100EP51DTGONMC10/100EP51 是一款具有重置功能的差分時鐘 D 類觸發(fā)器。該器件的功能與 EL51 和 LVEL51 器件相同。重置輸入為異步、電平觸發(fā)的信號。當時鐘為低電平時數(shù)據(jù)進入觸發(fā)器的主部分，然后傳輸?shù)綇牟糠?，并因此在時鐘發(fā)生正向轉(zhuǎn)換時傳輸?shù)捷敵?。EP51 的差分時鐘輸入允許該器件用作下降沿觸發(fā)的觸發(fā)器。差分輸入采用箝位電路來保持開路輸入條件下的穩(wěn)定性。保持開路時，CLK 輸入將下拉至 VEE，CLKbar 輸入將在 VCC / 2 處偏置。 立即購買

    技術(shù)資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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