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    首頁產(chǎn)品索引MC10EP90

    MC10EP90

    購買收藏
    ?Translator, Triple ECL Input to LVPECL / PECL Output

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10/100EP90 is a TRIPLE ECL TO LVPECL/PECL translator. The device receives differential LVECL or ECL signals and translates them to differential LVPECL or PECL output signals. A V
    output is provided for interfacing with single ended LVECL or ECL signals at the input. If a single ended input is to be used the V
    output should be connected to the D input. The active signal would then drive the D input. When used the V
    output should be bypassed to ground by a 0.01 F capacitor. The V
    output is designed to act as the switching reference for the EP90 under single ended input switching conditions, as a result this pin can only source/sink up to 0.5mA of current.
    To accomplish the level translation the EP90 requires three power rails. The V
    supply should be connected to the positive supply, and the V
    connected to the negative supply.
    The 100 Series contains temperature compensation.
    • 260 ps Typical Propagation Delay
    • Maximum Frequency > 3 GHz Typical
    • Voltage Supplies V
    • = 3.0 V to 5.5 V, V
    • = -3.0 V to -5.5 V, GND = 0 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Fully Differential Design
    • Q Output will default LOW with inputs open or at V
    • V
    • Output
    • These are Pb-Free Devices

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    型號制造商描述購買
    MC10EP90DTGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載

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