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    首頁產(chǎn)品索引MC100EPT622

    MC100EPT622

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    ?Translator, 10-bit LVTTL / LVCMOS to LVPECL

    制造商:ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100EPT622 is a 10-Bit LVTTL/LVCMOS to LVPECL translator.Because LVPECL (Positive ECL) levels are used, only +3.3 V and ground are required.The device has an OR-ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL).If the inputs are left open, they will default to the enable state.The device design has been optimized for low channel-to-channel skew.
    • 450 ps Typical Propogation Delay
    • Maximum Frequency > 1.5 GHz Typical
    • PECL Mode
    • Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • PNP LVTTL Inputs for Minimal Loading
    • Q Outputs Will Default HIGH with Inputs Open
    • The 100 Series Contains Temperature Compensation

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100EPT622MNGON 立即購買
    MC100EPT622FAGON 立即購買
    MC100EPT622FAR2GONIC XLATOR LVTTL/CMOS-PECL 32LQFP 立即購買

    技術資料

    標題類型大?。↘B)下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    Interfacing with ECLinPSPDF72 點擊下載
    Termination of ECL Logic DevicesPDF176 點擊下載

    應用案例更多案例

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