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    首頁產(chǎn)品索引MC100EPT26

    MC100EPT26

    購買收藏
    2 Fanout Differential LVPECL / LVDS to LVTTL

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC100EPT26 is a 1:2 Fanout Differential LVPECL to LVTTL translator. Because LVPECL (Positive ECL) levels are used only +3.3V and ground are required. The small outline 8-lead SOIC package and the 1:2 fanout design of the EPT26 makes it ideal for applications which require the low skew duplication of a signal in a tightly packed PC board.
    The V
    output allows the EPT26 to be used in a single-ended input mode. In this mode the V
    output is tied to the D0bar input for a non-inverting buffer or the D0 input for an inverting buffer. If used, the V
    pin should be bypassed to ground via a 0.01 uF capacitator.
    • 1.4ns Typical Propagation Delay
    • Maximum Frequency > 275 MHz Typical
    • The 100 Series Contains Temperature Compensation
    • Operating Range: V
    • = 3.0 V to 3.6 V with GND = 0 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • 24mA TTL outputs
    • Q Outputs will default LOW with inputs open or at V
    • V
    • Output
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號(hào)制造商描述購買
    MC100EPT26MNR4GON 立即購買
    MC100EPT26DR2GONIC XLATOR LVPECL-LVTTL 8-SOIC 立即購買
    MC100EPT26DTR2GON 立即購買
    MC100EPT26DTGON 立即購買
    MC100EPT26DGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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