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    首頁產(chǎn)品索引MC100ELT21

    MC100ELT21

    購買收藏
    ?Translator, Differential PECL to TTL

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10ELT/100ELT21 is a differential PECL to TTL translator. Because PECL (Positive ECL) levels are used, only +5 V and ground are required. The small outline 8-lead package and the single gate of the ELT21 makes it ideal for those applications where space, performance
    and low power are at a premium.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The 100 Series contains temperature compensation.
    • 3.5ns Typical Propagation Delay
    • 24mA TTL Output
    • Flow Through Pinouts
    • ESD Protection: > 2 KV HBM
    • Operating Range: V
    • = 4.75 V to 5.25 V with GND= 0 V
    • Q Output Will Default LOW with Inputs Left Open or
    • Internal Input Pulldown Resistors
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 81 devices
    • Pb-Free Packages are Available

    在線購買

    型號(hào)制造商描述購買
    MC100ELT21DTGONMixed Signal Translator Unidirectional 1 Circuit 1 Channel 8-TSSOP 立即購買
    MC100ELT21DTR2GONMixed Signal Translator Unidirectional 1 Circuit 1 Channel 8-TSSOP 立即購買
    MC100ELT21DR2GONMixed Signal Translator Unidirectional 1 Circuit 1 Channel 8-SOIC 立即購買
    MC100ELT21DGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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