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    首頁產(chǎn)品索引MC100EP451

    MC100EP451

    購買收藏
    ?3.3 V / 5.0 V ECL 6-Bit Differential Register with Master Reset

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10/100EP451 is a 6-bit fully differential register with common clock and single ended Master Reset (MR). It is ideal for very high frequency applications where a registered data path is necessary. All inputs have a 75k-ohm pulldown resistor internally. Differential inputs have an override clamp. Unused differential register inputs can be left open and will default LOW. When the differential inputs are forced to EE + 1.2 V, the clamp will override and force the output to a default state. When in the default state, and since the flip-flop is edge triggered, the output reaches a determined, but not predicted, valid state.
    The positive transition of CLK (pin 4) will latch the registers. Master Reset (MR) HIGH will asynchronously reset all registers forcing Q outputs to go LOW.
    The 100 Series contains temperature compensation.
    • 450 ps Typical Propagation Delay
    • Maximum Frequency > 3.0 GHz Typical
    • Asynchronous Master Reset
    • 20 ps Skew Within Device, 35 ps Skew Device-To-Device
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100EP451MNR4GON 立即購買
    MC100EP451MNGON 立即購買
    MC100EP451FAR2GONMC10/100EP451 是具有公用時鐘和單端主重置 (MR) 功能的 6 位全差分寄存器。該寄存器適用于需要注冊數(shù)據(jù)路徑的極高頻率應(yīng)用。所有輸入內(nèi)部都有一個 75k 歐姆的下拉電阻。差分輸入具有超控箝位。未使用的差分寄存器輸入可以保持開路，默認為 低電平。當差分輸入被強制為 立即購買
    MC100EP451FAGONMC10/100EP451 是具有公用時鐘和單端主重置 (MR) 功能的 6 位全差分寄存器。該寄存器適用于需要注冊數(shù)據(jù)路徑的極高頻率應(yīng)用。所有輸入內(nèi)部都有一個 75k 歐姆的下拉電阻。差分輸入具有超控箝位。未使用的差分寄存器輸入可以保持開路，默認為 低電平。當差分輸入被強制為 立即購買

    技術(shù)資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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