free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶:為給您持續(xù)提供一對(duì)一優(yōu)質(zhì)服務(wù),即日起,元器件訂單實(shí)付商品金額<300元時(shí),該筆訂單按2元/SKU加收服務(wù)費(fèi),感謝您的關(guān)注與支持!
    首頁產(chǎn)品索引TLC3548

    TLC3548

    購買收藏
    14 位、5V、200KSPS、8 通道單級(jí)性 ADC

    制造商:TI

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    描述The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital inputs [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter. CS\ can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on, and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS\ or FS) are needed to interface with the host. In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART\ to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power consumption. The power saving feature is further enhanced with software power-down/ autopower-down modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548 have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V external reference is used.特性14-Bit Resolution Maximum Throughput 200 KSPS Analog Input Range 0-V to Reference Voltage Multiple Analog Inputs: 8 Channels for TLC3548 4 Channels for TLC3544 Pseudodifferential Analog Inputs SPI/DSP-Compatible Serial Interfaces With SCLK up to 25 MHz Single 5-V Analog Supply; 3-/5-V Digital Supply Low Power: 4 mA (Internal Reference: 1.8 mA) for Normal Operation 20 μA in Autopower-Down Built-In 4-V Reference, Conversion Clock and 8x FIFO Hardware-Controlled and Programmable Sampling Period Programmable Autochannel Sweep and Repeat Hardware Default Configuration INL: ±1 LSB Max DNL: ±1 LSB Max SINAD: 80.8 dB THD: ?95 dB

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    TAJB106K016RNJTP5335TCP-5068UBTSC2000
    TPS61291TMS320C5532tda2030aTC7650
    TC53tip42cTC4421TLV1549
    TLC2558TMP05TLV2556TTH200W04TV1
    TDC1011-Q1THS10082TC1047TMMBAT43
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號(hào)工商網(wǎng)監(jiān)認(rèn)證 工商網(wǎng)監(jiān) 營業(yè)執(zhí)照