描述TI’s new TDA2Ex System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Ex family enables broad ADAS applications in today’s automobile by integrating an optimal mix of performance, low power, and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free driving experience. The TDA2Ex SoC enables sophisticated embedded vision technology in today’s automobile by enabling a board range of ADAS applications including park assist, surround view and sensor fusion on a single architecture. The TDA2Ex SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed and floating-point TMS320C66x digital signal processor (DSP) generation core, ARM Cortex-A15 MPCore? and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams over an Ethernet AVB network, along with graphics accelerator for rendering virtual views, enable a 3D viewing experience. The TDA2Ex SoC also integrates a host of peripherals including multicamera interfaces (both parallel and serial, including CSI-2) to enable Ethernet or LVDS-based surround view systems, displays and GigB Ethernet AVB. Additionally, TI provides a complete set of development tools for the ARM and DSP, including C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility into source code execution. The TDA2Ex ADAS processor is qualified according to the AEC-Q100 standard.特性Architecture Designed for ADAS Applications Video, Image, and Graphics ProcessingSupportFull-HD Video (1920 × 1080p, 60 fps) Multiple Video Input and Video OutputARM? Cortex?-A15 Microprocessor Subsystem C66x Floating-Point VLIW DSPFully Object-Code Compatible With C67x and C64x+ Up to Thirty-two 16 × 16-Bit Fixed-Point Multiplies per Cycle Up to 512KB of On-Chip L3 RAM Level 3 (L3) and Level 4 (L4)InterconnectsDDR3/DDR3L Memory Interface (EMIF)ModuleSupports up to DDR3-1333 (667 MHz) Up to 2GB Across Single Chip Select Dual ARM?Cortex?-M4 Image Processing Units (IPU) IVA-HD Subsystem DisplaySubsystemDisplay Controller With DMA Engine and up to Three Pipelines HDMI? Encoder: HDMI 1.4a and DVI 1.0 Compliant Single-Core PowerVR? SGX544 3DGPU 2D-Graphics Accelerator (BB2D) SubsystemVivante? GC320 CoreVideo Processing Engine (VPE) One Video Input Port (VIP) ModuleSupport for up to Four Multiplexed Input PortsGeneral-Purpose Memory Controller (GPMC)Enhanced Direct Memory Access (EDMA) Controller 2-Port Gigabit Ethernet (GMAC)Up to Two External Ports, One InternalSixteen 32-Bit General-Purpose Timers32-Bit MPU Watchdog Timer Six High-Speed Inter-Integrated Circuit (I2C)Ports TenConfigurable UART/IrDA/CIR Modules Four Multichannel Serial Peripheral Interfaces (McSPI) QuadSPI Interface (QSPI) SATA InterfaceEight Multichannel Audio Serial Port (McASP)Modules SuperSpeed USB 3.0 Dual-Role Device High-Speed USB2.0 Dual-Role Device High-Speed USB 2.0 On-The-Go Four MultiMedia Card/Secure Digital/Secure Digital InputOutput Interfaces (MMC/SD/SDIO)PCI Express? 3.0 Port With IntegratedPHYOne 2-lane Gen2-Compliant Port or Two 1-lane Gen2-Compliant Ports Dual Controller Area Network (DCAN)ModulesCAN 2.0B ProtocolMIPI CSI-2Camera Serial Interface Up to 215General-Purpose I/O (GPIO) Pins Real-Time Clock Subsystem (RTCSS) Device Security FeaturesHardware Crypto Accelerators and DMA Firewalls JTAG Lock Secure Keys Secure ROM and BootPower,Reset, and Clock ManagementOn-Chip Debug With CTools Technology 28-nm CMOSTechnology23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABC)