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    首頁產(chǎn)品索引NB6N239S

    NB6N239S

    購買收藏
    ?3.3 V Any Differential Clock to LVDS, ÷·1/2/4/8 and ÷·2/4/8/16 Clock Divider

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The NB6N239S is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; Div1/2/4/8 and Div 2/4/8/16. Both divider circuits drive LVDS compatible outputs. The NB6N239S is a member of the ECLinPS MAX
    family of high performance clock products.
    • Maximum Clock Input Frequency, 3.0 GHz (1.5 GHz with Div 1)
    • Input Compatible with LVDS/LVPECL/CML/HSTL
    • 120ps Typical Rise/Fall Times
    • Example; 622.08 MHz Input Generates 38.88 MHz to 622.08 MHz outputs
    • Internal 50Ω Termination Provided
    • Divide-by-1 Edge of QA Aligned to QB Divided Output
    • Operating Range: V
    • = 3.0 V to 3.465V with GND = 0
    • Master Reset for Synchronization of Multiple Chips
    • V
    • Reference Output
    • Synchronous Output Disable/Enable
    • Pb-Free Packages are Available

    在線購買

    型號制造商描述購買
    NB6N239SMNR2GONIC CLOCK DIVIDER DIFF LVDS 16QFN 立即購買
    NB6N239SMNGONIC CLOCK DIVIDER 3.3V 16-QFN 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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