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    首頁產品索引NB100LVEP222

    NB100LVEP222

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    15 Differential, ÷1 / ÷2, ECL / PECL, 2.5 V / 3.3 V

    制造商:ON

    中文數(shù)據(jù)手冊

    產品信息

    The NB100LVEP222 is a low skew 2:1:15 differential div 1/div 2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. When the output banks are configured with the div 1 mode, data can also be distributed. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 4). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC/VCC0 supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in 2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC/VCC0 via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open
    • 20 ps Output-to-Output Skew
    • 85 ps Part-to-Part Skew
    • Selectable 1x or 1/2x Frequency Outputs
    • LVPECL Mode Operating Range: V
    • = 2.375 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -2.375 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Performance Upgrade to ON Semiconductor's MC100LVE222
    • V
    • Output

    電路圖、引腳圖和封裝圖

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    型號制造商描述購買
    NB100LVEP222MNGONNB100LVEP222 是一款低歪曲率 2:1:15 差分 1 分頻/2 分頻 ECL 扇出緩沖器,適用于時鐘分發(fā)。LVECL/LVPECL 輸入信號對可用于差分配置或單端(VBB 輸出參考旁通并聯(lián)接一對未使用輸入)??梢赃x擇兩個全差分時鐘輸入之一。在由 2、3、4 和 6 個差分對組成的四個輸出組中,每組均可獨立配置為輸入頻率的扇出 1X 或 1/2X。當輸出組配置為 1 分頻模式時,數(shù)據(jù)也可進行分發(fā)。LVEP222 可特別保證低輸出-輸出歪曲率。優(yōu)化的設計、布局和處理最大程度降低了器件內和批次與批次之間的歪曲率。此器件是 MC100LVE222 的改善版本,具有更高速度能力且降低了歪曲率。fsel 引腳和 CLK_Sel 引腳為異步控制輸入。任何更改都可能導致不確定的輸出狀態(tài),需要 MR 脈沖來重新同步任何 1/2X 輸出(參見圖 4)。未使用的輸出對應保持未端接(開路)以降低功耗和開關噪聲。NB100LVEP222 與大多數(shù) ECL 器件相同,可以 LVPECL 模式,基于正 VCC/VCC0 電源運行。因此,在 2.5/3.3 V 系統(tǒng)中使用 LVEP222 可實現(xiàn)高性能的時鐘分發(fā)。在 PECL 環(huán)境串聯(lián)或戴維南線路中,通常使用端接,因為它們無需額外的電源。有關使用 PECL 的更多信息,設計人員應參考應用說明 AN1406/D。 有關 SPICE 信號,請參考應用說明 AN1560/D。 僅為此器件提供 VBB 引腳,即內部產生的供應電壓。對于單端 LVPECL 輸入的情況,將未使用的差分輸入聯(lián)接至 VBB,作為開關參考電壓。VBB 還可將 AC 耦合輸入重偏置。使用時,通過一個 0.01 uF 電容將 VBB 和 VCC/VCC0 去耦合,并限制電流源或接收 0.5 mA 的電流。不使用時,VBB 應保持開路。 立即購買
    NB100LVEP222MNRGONIC CLK BUFFER 1:15 1GHZ 立即購買

    技術資料

    標題類型大?。↘B)下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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