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    首頁產品索引NB6L239

    NB6L239

    購買收藏
    ?2.5 V / 3.3 V Any Differential Clock In to Differential LVPECL Out

    制造商：ON

    中文數據手冊

    產品信息

    The NB6L239 is a high-speed, low skew clock divider with two divider circuits, each having selectable clock divide ratios; divide 1/2/4/8 and divide 2/4/8/16. Both divider circuits drive a pair of LVPECL outputs
    • Maximum Clock Input Frequency; ≥ 3GHz
    • Input compatibility with LVDS/LVPECL/CML/HSTL
    • 70 ps Typical Rise/Fall Times
    • 5 ps Typcial Output-to-Output Skew
    • Ex. 622.08MHz Input Generates 38.88MHz to 622.08 MHz Outputs
    • Internal 50 Ω Termination Provided
    • Random Clock Jitter ≤ 1 ps RMS
    • Divide-by-1 Edge of QA Aligned to QB divided Output
    • Operating Range: V
    • = 2.375 V to 3.465 V with V
    • = 0 V
    • Master Reset for Synchronization of Multiple Chips
    • V
    • Reference Output
    • Synchronous Output Disable/Enable
    • Telecom/Datacom Routers, Swithes
    • Pb-Free Packages are Available

    在線購買

    型號制造商描述購買
    NB6L239MNR2GONIC CLOCK DIVIDER HS 16-QFN 立即購買
    NB6L239MNGONIC CLOCK DIVIDER HS 16-QFN 立即購買

    技術資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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