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    首頁產(chǎn)品索引NB3W1900L

    NB3W1900L

    購買收藏
    19 HCSL-Compatible Push‐Pull Clock ZDB/Fanout Buffer for PCIe

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The NB3W1900L differential clock buffers are designed to work inconjunction with a PCIe compliant source clock synthesizer to providepoint-to-point clocks to multiple agents. The device is capable ofdistributing the reference clocks for Intel? QuickPath Interconnect(Intel QPI & UPI), PCIe Gen1/Gen2/Gen3/Gen4.The NB3W1900L internal PLL isoptimized to support 100MHz and 133 MHz frequency operation.The NB3W1900L is developed with the low-power NMOS Push-Pullbuffer type.
    • 19 Low Power Differential Clock Output Pairs @ 0.7 V
    • Output-to-Output Skew Performance:
    • Cycle-to-Cycle Jitter (PLL Mode):
    • 100 MHz and 133 MHz PLL Mode to Meet the Next Generation PCIe Gen2/ Gen3/ Gen4 and Intel QPI & UPI Phase Jitter
    • Input-to-Output Delay Variation:
    • Fixed-Feedback for Lowest Input-to-Output Delay Variation
    • Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI
    • Individual OE Control via SMBus
    • Low-Power NMOS Push-Pull HCSL?Compatible Outputs
    • PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation)
    • SMBus Address Configurable to Allow Multiple Buffers in a Single Control Network
    • Programmable PLL Bandwidth
    • Two Tri-level Addresses Selection (Nine SMBus Addresses)
    • QFN 72-pin Package, 10 mm × 10 mm
    • These are Pb-Free Devices

    在線購買

    型號制造商描述購買
    NB3W1900LMNGON 立即購買
    NB3W1900LMNTXGON 立即購買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    QFN72 10x10, 0.5PPDF56 點擊下載
    3.3 V 100 MHz/133 MHz Differential 1:19 HCSL-Compatible Push-Pull Clock ZDB/Fanout Buffer forPCIe PDF175 點擊下載
    NB3W1900L IBIS ModelUNKNOW64 點擊下載
    A System Designer"s Guide for Building a PCIe Clock Tree while Addressing Timing ChallengesPDF179 點擊下載

    應(yīng)用案例更多案例

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