free性丰满hd毛多多,久久综合给合久久狠狠狠97色69 ,欧美成人乱码一区二区三区,国产美女久久久亚洲综合,7777久久亚洲中文字幕

尊敬的客戶:為給您持續(xù)提供一對(duì)一優(yōu)質(zhì)服務(wù),即日起,元器件訂單實(shí)付商品金額<300元時(shí),該筆訂單按2元/SKU加收服務(wù)費(fèi),感謝您的關(guān)注與支持!
    首頁產(chǎn)品索引NB3L208K

    NB3L208K

    購買收藏
    8 HCSL Fanout Buffer

    制造商:ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NB3L208K is a differential 1:8 Clock fanout buffer withHigh?speed Current Steering Logic (HCSL) outputs. Inputs candirectly accept differential LVPECL, LVDS, and HCSL signals.Single?ended LVPECL, HCSL, LVCMOS, or LVTTL levels areaccepted with a proper external Vth reference supply per Figures 4and 6. The input signal will be translated to HCSL and provides eightidentical copies operating up to 350 MHz.The NB3L208K is optimized for ultra?low phase noise, propagationdelay variation and low output–to–output skew, and is DB800Hcompliant. As such, system designers can take advantage of theNB3L208K’s performance to distribute low skew clocks across thebackplane or the motherboard making it ideal for Clock and Datadistribution applications such as PCI Express, FBDIMM, Networking,Mobile Computing, Gigabit Ethernet, etc.Output drive current is set by connecting a 475resistor fromIREF (Pin 27) to GND per Figure 11. Outputs can also interface toLVDS receivers when terminated per Figure 12.
    • Maximum Input Clock Frequency > 350 MHz
    • 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
    • 8 HCSL Outputs
    • DB800H Compliant
    • Individual OE Control Pin for Each Bank of 2 Outputs
    • 100 ps Max Output?to?Output Skew Performance
    • 1 ns Typical Propagation Delay
    • 450 ps Typical Rise and Fall Times
    • 80 fs Maximum Additive Phase Jitter RMS

    在線購買

    型號(hào)制造商描述購買
    NB3L208KMNGONNB3L208K 是一款差分 1:8 時(shí)鐘扇出緩沖器,帶高速電流轉(zhuǎn)向 (HCSL) 輸出。輸入可直接接受差分 LVPECL、LVDS 和 HCSL 信號(hào)。使用恰當(dāng)?shù)耐獠?Vth 參考電源,接受單端 LVPECL、HCSL、LVCMOS 或 LVTTL 電平,參見圖 4 和 6。 輸入信號(hào)將轉(zhuǎn)換為 HCSL,能夠運(yùn)行頻率最高 350 MHz 的八個(gè)相同版本。NB3L208K 針對(duì)超低相位干擾、傳播延遲變化和低輸出-輸出歪曲率進(jìn)行了優(yōu)化,符合 DB800H 標(biāo)準(zhǔn)。因此,系統(tǒng)設(shè)計(jì)人員可以利用 NB3L208K 的性能在背面電極或母板中分發(fā)低歪曲率時(shí)鐘,因此適用于 PCI Express、FBDIMM、聯(lián)網(wǎng)、移動(dòng)計(jì)算、千兆位以太網(wǎng)等時(shí)鐘和數(shù)據(jù)分發(fā)應(yīng)用。輸出驅(qū)動(dòng)電流通過從 IREF(引腳 27)到 GND 聯(lián)接一個(gè) 475 電阻來設(shè)置,如圖 11 所示。輸出端接時(shí)還可接口到 LVDS 接收器,如圖 12 所示。 立即購買
    NB3L208KMNTXGONNB3L208K 是一款差分 1:8 時(shí)鐘扇出緩沖器,帶高速電流轉(zhuǎn)向 (HCSL) 輸出。輸入可直接接受差分 LVPECL、LVDS 和 HCSL 信號(hào)。使用恰當(dāng)?shù)耐獠?Vth 參考電源,接受單端 LVPECL、HCSL、LVCMOS 或 LVTTL 電平,參見圖 4 和 6。 輸入信號(hào)將轉(zhuǎn)換為 HCSL,能夠運(yùn)行頻率最高 350 MHz 的八個(gè)相同版本。NB3L208K 針對(duì)超低相位干擾、傳播延遲變化和低輸出-輸出歪曲率進(jìn)行了優(yōu)化,符合 DB800H 標(biāo)準(zhǔn)。因此,系統(tǒng)設(shè)計(jì)人員可以利用 NB3L208K 的性能在背面電極或母板中分發(fā)低歪曲率時(shí)鐘,因此適用于 PCI Express、FBDIMM、聯(lián)網(wǎng)、移動(dòng)計(jì)算、千兆位以太網(wǎng)等時(shí)鐘和數(shù)據(jù)分發(fā)應(yīng)用。輸出驅(qū)動(dòng)電流通過從 IREF(引腳 27)到 GND 聯(lián)接一個(gè) 475 電阻來設(shè)置,如圖 11 所示。輸出端接時(shí)還可接口到 LVDS 接收器,如圖 12 所示。 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B)下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Clock Generation and Clock and Data Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)PDF40 點(diǎn)擊下載
    QFN32, 5x5, 0.5P, 3.1x3.1EPPDF56 點(diǎn)擊下載
    2.5V, 3.3V Differential 1:8 HCSL Fanout BufferPDF200 點(diǎn)擊下載
    NB3L208K IBIS ModelUNKNOW28 點(diǎn)擊下載
    NB3L208K IBIS ModelUNKNOW30 點(diǎn)擊下載
    NB3L208K Evaluation Board User"s ManualPDF424 點(diǎn)擊下載

    應(yīng)用案例更多案例

    系列產(chǎn)品索引查看所有產(chǎn)品

    NUF2450NV25160NB3H5150NCP1631
    NVMFD5C680NLNCP392BNCL30030NC7SP38
    NCV8130NB7L572NSM4002MR6NLSV4T3234
    NCS20082NB7LQ572NCS20091NCP2820
    NB3L853141NCS3402NC7SP126NCP1562
    Copyright ?2012-2025 hqchip.com.All Rights Reserved 粵ICP備14022951號(hào)工商網(wǎng)監(jiān)認(rèn)證 工商網(wǎng)監(jiān) 營業(yè)執(zhí)照