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    首頁(yè)產(chǎn)品索引MC10E1652

    MC10E1652

    購(gòu)買收藏
    ?Comparator, Dual, ECL Output with Latch

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10E1652 comparator is fabricated using ON Semiconductor's advanced MOSAIC III process and is output compatible with 10H logic devices. In addition, the device is available in both a 16-pin DIP and a 20-pin surface mount package. However, the MC10E1652 provides user programmable hysteresis.
    The latch enable (LENabar and LENbbar) input pins operate from standard ECL 10H logic levels. When the latch enable is at a logic high level, the MC10E1652 acts as a comparator; hence, Q will be at a logic high level if V1 > V2 (V1 is more positive than V2). Qbar is the complement of Q. When the latch enable input goes to a low logic level, the outputs are latched in their present state, providing the latch enable setup and hold time constraints are met. The level of input hysteresis is controlled by applying a bias voltage to the HYS pin.
    The 100 Series contains temperature compensation.
    • Typical 3.0 dB Bandwidth > 1.0 GHz
    • Typical V to Q Propagation Delay of 775 ps
    • Typical Output Rise/Fall of 350 ps
    • Common Mode Range -2.0 V to +3.0 V
    • Individual Latch Enables
    • Differential Outputs
    • Operating Mode: V
    • = 5.0 V, V
    • = -5.2 V
    • Programmable Input Hysteresis
    • No Internal Input Pulldown Resistors
    • ESD Protection: > 2 KV HBM, > 100 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 85 devices

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    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10E1652FNR2ONMAGNITUDE COMPARATOR 立即購(gòu)買
    MC10E1652FNONMAGNITUDE COMPARATOR 立即購(gòu)買
    MC10E1652FNGONMAGNITUDE COMPARATOR 立即購(gòu)買
    MC10E1652FNR2GONMAGNITUDE COMPARATOR 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載
    Clock Generation and Clock and Data Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    ECLinPS and ECLinPS Lite SPICE I/O Modeling KitPDF120 點(diǎn)擊下載
    5V Dual ECL Output Comparator With LatchPDF123 點(diǎn)擊下載
    IBIS Model for MC10E1652FNUNKNOW10 點(diǎn)擊下載
    20 LEAD PLLCPDF59 點(diǎn)擊下載

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