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    首頁(yè)產(chǎn)品索引MC100LVEL01

    MC100LVEL01

    購(gòu)買收藏
    ?ECL4-Input OR/NOR Gate

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC100LVEL01 is a 4-input OR/NOR gate. The device is functionally equivalent to the EL01 device and works from a -3.3V supply. With AC performance similar to the EL01 device, the LVEL01 is ideal for low voltage applications which require the ultimate in AC performance.
    • 370ps Propagation Delay
    • High Bandwidth Output Transitions
    • ESD Protection: >2 KV HBM, >200 V MM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Q Output will Default LOW with All Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 83 devices
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC100LVEL01DGONNOR/OR Gate Configurable 1 Circuit 4 Input 8-SOIC 立即購(gòu)買
    MC100LVEL01DTGONNOR/OR Gate Configurable 1 Circuit 4 Input 8-TSSOP 立即購(gòu)買
    MC100LVEL01DR2GON 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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