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    首頁產(chǎn)品索引MC100EP195B

    MC100EP195B

    購買收藏
    ?3.3 V ECL Programmable Delay Chip

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. Thedelay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D(9:0) values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D(9:0). A LOW to HIGH transition on LEN will LOCK and HOLD currentvalues present against any subsequent changes in D(10:0). The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3.
    • Maximum Input Clock Frequency >1.2 GHz Typical
    • Programmable Range: 0 ns to 10 ns
    • Delay Range: 2.2 ns to 12.2 ns
    • 10 ps Increments
    • PECL Mode Operating Range:VCC = 3.0 V to 3.6 V with VEE = 0 V
    • NECL Mode Operating Range:VCC = 0 V with VEE = 3.0 V to 3.6 V
    • IN/INb Inputs Accept LVPECL, LVNECL, LVDS Levels
    • A Logic High on the EN Pin Will Force Q to Logic Low
    • D10:0 Can Select Either LVPECL, LVCMOS, or LVTTL Input Levels
    • VBB Output Reference Voltage

    在線購買

    型號制造商描述購買
    MC100EP195BFAR2GONIC DELAY LN 1024TAP PROG 32LQFP 立即購買
    MC100EP195BMNR4GONIC DELAY LINE 1024TAP PROG 32QFN 立即購買
    MC100EP195BMNGONMC100EP195B 是一款可編程延遲芯片 (PDC)，主要用于時鐘去歪曲和計時調(diào)整。它提供了差分 NECL/PECL 輸入轉(zhuǎn)換的可變延遲。 延遲部分由一個可編程的門極和多工器矩陣組成，如圖 2 邏輯圖所示。 EP195B 延遲增量的可數(shù)字選擇分辨率約為 10 ps，凈范圍最高 10.2 ns。所需延遲由 10 個數(shù)據(jù)選擇輸入 D(9:0) 值選擇，由 LEN（引腳 10）控制。LEN 上的低電平可實現(xiàn) D(9:0) 確定的實時延遲值的透明加載模式。LEN 上的低電平-高電平轉(zhuǎn)換將針對 D(10:0) 中的 任何后續(xù)變化鎖定并保持現(xiàn)有電流值。表 6 和圖 3 中顯示了與 D0 (LSB) 至 D9 (MSB) 相關(guān)聯(lián)的各種抽頭數(shù)的恰當延遲值。 立即購買
    MC100EP195BFAGONIC DELAY LN 1024TAP PROG 32LQFP 立即購買

    技術(shù)資料

    標題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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