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    首頁產(chǎn)品索引MC100EP16VC

    MC100EP16VC

    購買收藏
    ?Differential Driver / Receiver with High Gain and Enable Output

    制造商:ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The EP16VC is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 and LVEP16 devices but with high gain and enable output.
    The EP16VC provides an ENbar input which is synchronized with the data input (D) signal in a way that provides litchless gating of the Q
    and Q
    bar outputs.
    When the ENbar signal is LOW, the input is passed to the outputs and the data output equals the data input. When the data input is HIGH and ENbar goes HIGH, it will force the Q
    LOW and the Q
    bar HIGH on the next negative transition of the data input. If the data input is LOW when the ENbar goes HIGH, the next data transition to a HIGH is ignored and Q
    remains LOW and Q
    bar remains HIGH. The next positive transition of the data input is not passed on to the data outputs under these conditions. The Q
    and Q
    bar outputs remain in their disabled state as long as the ENbar input is held HIGH or LOW. The ENbar input has no influence on the Qbar output and the data input is passed on (inverted) to this output whether ENbar is HIGH or LOW. This configuration is ideal for crystal oscillator applications where the oscillator can be free running and gated on and off synchronously without adding extra counts to the output.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The 100 Series contains temperature compensation.
    • 310 ps Typical Prop Delay Qbar, 380 ps Typical Prop Delay QHG, QHGbar
    • Gain > 200
    • Maximum Frequency > 3 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = –3.0 V to –5.5 V
    • Open Input Default State
    • Q
    • Output Will Default LOW with D inputs Open or at V
    • V
    • Output

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100EP16VCDTR2GON 立即購買
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    技術(shù)資料

    標(biāo)題類型大?。↘B)下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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