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    首頁產品索引MC100EP131

    MC100EP131

    購買收藏
    ?Quad D Flip-Flop with Set, Reset, and Differential Clock

    制造商：ON

    中文數(shù)據(jù)手冊

    產品信息

    The MC10EP131 is a Quad Master-slaved D flip-flop with common set and separate resets. The device is an expansion of the E131 with differential common clock and individual clock enables. With AC performance faster than the E131 device, the EP131 is ideal for applications requiring the fastest AC performance available.
    Each flip-flop may be clocked separately by holding Common Clock (C
    ) LOW and (C
    bar) HIGH, then using the Clock Enable inputs for clocking (C
    and C
    bar).
    Common clocking is achieved by holding the C
    inputs LOW and C
    bar inputs HIGH while using the differential common clock C
    to clock all four flip-flops. When left floating open, any differential input will disable operation due to input pulldown resistors forcing an output default state.
    Individual asynchronous resets (R
    ) and an asynchronous set (SET) are provided.
    Data enters the master when both C
    and C
    are LOW, and transfers to the slave when either C
    or C
    (or both) go HIGH.
    The 100 Series contains temperature compensation.
    • 460ps Typical Propagation Delay
    • Maximum Frequency > 3 GHz Typical
    • Differential Individual and Common Clocks
    • Individual Asynchronous Resets
    • Asynchronous Set
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • Pb-Free Packages are Available

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    在線購買

    型號制造商描述購買
    MC100EP131MNGON 立即購買
    MC100EP131FAR2GON 立即購買
    MC100EP131FAGON 立即購買

    技術資料

    標題類型大?。↘B）下載
    Interfacing with ECLinPSPDF72 點擊下載
    Termination of ECL Logic DevicesPDF176 點擊下載
    Thermal Analysis and Reliability of WIRE BONDED ECLPDF119 點擊下載
    Clock Generation and Clock and Data Marking and Ordering Information GuidePDF71 點擊下載
    Phase Lock Loop General OperationsPDF64 點擊下載
    IBIS Model for MC100EP131FA VCC at 3.3 VUNKNOW6 點擊下載
    3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential ClockPDF164 點擊下載
    QFN32, 5x5, 0.5P, 3.1x3.1EPPDF56 點擊下載

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