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    首頁(yè)產(chǎn)品索引MC100EP116

    MC100EP116

    購(gòu)買(mǎi)收藏
    ?Differential Line Receiver / Driver

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10EP116/100EP116 is a 6-bit differential line receiver based on the EP16 device. The 3.0GHz bandwidth provided by the high frequency outputs makes the device ideal for buffering of very high speed oscillators.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.
    The differential inputs have internal clamp structures which will force the Q output of a gate in an open input condition to go to a LOW state. Thus, inputs of unused gates can be left open and will not affect the operation of the rest of the device. Note that the input clamp will take affect only if both inputs fall 2.5V below V
    .
    The 100 Series contains temperature compensation.
    • 260 ps Typical Propagation Delay
    • Maximum Frequency > 3 GHz Typical
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • =-3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • Q Output will default LOW with inputs open or at V
    • V
    • Output

    電路圖、引腳圖和封裝圖

    在線購(gòu)買(mǎi)

    型號(hào)制造商描述購(gòu)買(mǎi)
    MC100EP116FAR2GONIC TCVR/DRVR HEX DIFF ECL 32LQFP 立即購(gòu)買(mǎi)
    MC100EP116FAGON 立即購(gòu)買(mǎi)

    技術(shù)資料

    標(biāo)題類(lèi)型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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