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    首頁產(chǎn)品索引MC100EL56

    MC100EL56

    購買收藏
    1 Differential, Dual ECL, 5.0 V

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100EL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple V
    pins are provided to ease AC coupling input signals.
    The V
    pins, an internally generated voltage supply, are available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The device features both individual and common select inputs to address both data path and random logic applications.
    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open, the D input will pull down to V
    . The D input will bias around V
    /2 forcing the Q output LOW.
    • 580 ps Typical Propagation Delays
    • Separate and Common Select
    • ESD Protection: > 2 KV HBM, > 100 V MM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors on D(s), SEL(s), and COM_SEL
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 147 devices
    • Pb-Free Packages Are Available

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    型號制造商描述購買
    MC100EL56DWR2GONIC DIFF DIG MULTPL 2X2:1 20SOIC 立即購買
    MC100EL56DWGONIC DIFF DIG MULTPL 2X2:1 20SOIC 立即購買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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