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    首頁(yè)產(chǎn)品索引74LVC373

    74LVC373

    購(gòu)買收藏
    ?Low Voltage CMOS Octal Transparent Latch

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The 74LVC373A is a high performance, non-inverting octal transparent latch operating from a 1.2 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V
    specification of 5.5 V allows 74LVC373A inputs to be safely driven from 5 V devices. The 74LVC373A contains 8 D-type latches with 3-state outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OEbar) input. When OEbar is LOW, the standard outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.
    • Designed for 1.2 to 3.6 V V
    • Operation
    • 5 V Tolerant ? Interface Capability With 5 V TTL Logic
    • Supports Live Insertion and Withdrawal
    • I
    • Specification Guarantees High Impedance When V
    • = 0 V
    • 24 mA Output Sink and Source Capability
    • Near Zero Static Supply Current in all Three Logic States (10 μA) Substantially Reduces System Power Requirements
    • Latch-up Performance Exceeds 250 mA
    • ESD Performance: Human Body Model >2000 V; Machine Model >200 V
    • These Devices are Pb?Free, Halogen Free/BFR Free and are RoHS Compliant

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    74LVC373ADTR2GONICTRANSPARENTLATCH20TSSOP 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    TSSOP-20 WBPDF38 點(diǎn)擊下載
    Low Voltage CMOS Octal Transparent LatchPDF93 點(diǎn)擊下載

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