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    首頁產(chǎn)品索引NB7V586M

    NB7V586M

    購買收藏
    6 CML, 1.2 V / 1.8 V

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The NB7V586M is a differential 1-to-6 CML Clock/Data Distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INxb inputs incorporate internal 50-ohm termination resistors and will accept differential LVPECL, CML, or LVDS logic levels. The INx/INxb inputs and core logic are powered with a 1.8 V supply. The NB7V586M produces six identical differential CML output copies of Clock or Data. The outputs are configured as three banks of two differential pair. Each bank (or all three banks) have the flexibility of being powered by any combination of either a 1.8 V or 1.2 V supply. The 16 mA differential CML output structure provides matching internal 50-ohm source terminations and 400 mV output swings when externally terminated with a 50-ohm resistor to VCCOx. The 1:6 fanout design was optimized for low output skew and minimal jitter and is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock/Data distribution applications operating up to 6 GHz or 10 Gb/s typical. The VREFAC reference outputs can be used to rebias capacitor-coupled differential or single-ended input signals. The NB7V586M is offered in a low profile 5mm x 5mm 32-pin Pb-Free QFN package.
    • Maximum Input Data Rate > 10 Gb/s Typical
    • Data Dependent Jitter
    • Maximum Input Clock Frequency > 6 GHz Typical
    • Random Clock Jitter
    • Low Skew 1:6 CML Outputs, 30 ps Max
    • 2:1 MultiLevel Mux Inputs
    • 175 ps Typical Propagation Delay
    • 50 ps Typical Rise and Fall Times
    • Differential CML Outputs, 330 mV PeaktoPeak, Typical
    • Operating Range: VCC = 1.71 V to 1.89 V; VCCOx = 1.14 V to 1.89 V
    • Internal 50-ohm Input Termination Resistors
    • VREFAC Reference Output
    • 40C to +85C Ambient Operating Temperature

    在線購買

    型號制造商描述購買
    NB7V586MMNGON 立即購買
    NB7V586MMNR4GONNB7V586M 是一款 1:6 CML 時(shí)鐘/數(shù)據(jù)分發(fā)芯片，具有 2:1 時(shí)鐘/數(shù)據(jù)輸入多工器，帶輸入選擇引腳。INx/INxb 輸入包含內(nèi)部 50 Ω 端接電阻，并接受差分 LVPECL、CML 或 LVDS 邏輯電平。INx/INxb 輸入和核芯邏輯由 1.8 V 電源供電。NB7V586M 產(chǎn)生時(shí)鐘或數(shù)據(jù)的六個(gè)相同的差分 CML 輸出副本。輸出配置為三組兩個(gè)差分對。每組（或所有三組）均能通過 1.8 V 或 1.2 V 電源的任意組合供電。當(dāng)外部接收器以 50 Ω 電阻端接到 VCCOx 時(shí)，16 mA 差分 CML 輸出結(jié)構(gòu)提供匹配的內(nèi)部 50 Ω 源端接和 400 mV 輸出擺幅。1:6 扇出設(shè)計(jì)針對低輸出歪曲率和最小抖動(dòng)而優(yōu)化，適用于 SONET、GigE、光纖信道、背面電極，以及運(yùn)行典型值高達(dá) 6 GHz 或 10 Gb/s 的其他時(shí)鐘/數(shù)據(jù)分發(fā)應(yīng)用。VREFAC 參考輸出可用于重新偏置電容器耦合的差分和單端輸入信號。NB7V586M 采用小巧的 5mm x5mm 32 引腳 QFN 無鉛封裝。 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer /TranslatorPDF134 點(diǎn)擊下載
    IBIS Model for NB7V586MUNKNOW41 點(diǎn)擊下載
    QFN32, 5x5, 0.5P, 3.1x3.1EPPDF56 點(diǎn)擊下載

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