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    首頁產(chǎn)品索引NB4L52

    NB4L52

    購買收藏
    ?2.5 to 5.5 V ECL D Flip-flop w/Differential Reset & Input Termination

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The NB4L52 is a differential Data and Clock D flip?flop with a differential asynchronous Reset. The differential inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock transitions from Low to High, Data will be transferred to the differential LVPECL outputs. The differential Clock inputs allow the NB4L52 to also be used as a negative edge triggered device. The device is housed in a small 3mm x 3mm 16 pin QFN package.
    • Maximum Input Clock Frequency > 4 GHz Typical
    • 330 ps Typical Propagation Delay
    • 145 ps Typical Rise and Fall Times
    • Differential LVPECL Outputs, 750 mV PeaktoPeak, Typical
    • Operating Range: VCC = 2.375 V to 5.5 V with VEE = 0 V

    在線購買

    型號制造商描述購買
    NB4L52MNR2GONNB4L52 是一款差分?jǐn)?shù)據(jù)和時(shí)鐘 D 觸發(fā)器，帶差分異步重置。差分輸入結(jié)合了內(nèi)部 50 Ω 端接電阻，接受 LVPECL、LVCMOS、LVTTL、CML 或 LVDS 邏輯電平。當(dāng)時(shí)鐘從低電平轉(zhuǎn)換為高電平時(shí)，數(shù)據(jù)將傳輸?shù)讲罘?LVPECL 輸出。差分時(shí)鐘輸入使得 NB4L52 還能用作負(fù)邊沿觸發(fā)器件。該器件采用小型 3mm x 3mm 16 引腳 QFN 封裝。 立即購買
    NB4L52MNGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    IBIS Model for the NB4L52MN UNKNOW36 點(diǎn)擊下載
    QFN16, 3x3, 0.5PPDF55 點(diǎn)擊下載

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