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    首頁(yè)產(chǎn)品索引NB3N502

    NB3N502

    購(gòu)買收藏
    ?PLL Clock Multiplier, 14 MHz - 190 MHz, 3.3 V / 5.0 V

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NB3N502 is a clock multiplier device that generates a low jitter,TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The device is a cost efficient replacement for the crystal oscillators commonly used in electronic systems. It accepts a standard fundamental mode crystal or an external reference clock signal. Phase-Locked-Loop (PLL) design techniques are used to produce an output clock up to 190 MHz with a 50% duty cycle. The NB3N502 can be programmed via two select inputs (S0, S1) to provide an output clock (CLKOUT) at one of six different multiples of the input frequency source, and at the same time output the input aligned reference clock signal (REF).
    • Clock Output Frequency up to 190 MHz
    • Operating Range: VDD = 3 V to 5.5 V
    • Low Jitter Output of 15 ps One Sigma (RMS)
    • Zero ppm Clock Multiplication Error
    • 45%55% Duty Cycle
    • Crystal Reference Input Range of 5 MHz to 27 MHz
    • Input Clock Frequency Range of 2 MHz to 50 MHz
    • Full Industrial Temperature Range -40C to 85C

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    NB3N502DR2GON 立即購(gòu)買
    NB3N502DGON 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    PLL Clock Multiplier, 14 MHz - 190 MHz, 3.3 V / 5.0 VPDF133 點(diǎn)擊下載
    IBSUI model for NB3N502 3.3VUNKNOW5 點(diǎn)擊下載
    IBIS Model for NB3N502 5.0VUNKNOW5 點(diǎn)擊下載
    SOIC-8 Narrow BodyPDF61 點(diǎn)擊下載
    NB3N502DEVB Evaluation Board User"s ManualPDF247 點(diǎn)擊下載

    應(yīng)用案例更多案例

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