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    首頁產(chǎn)品索引NB3M8T3910G

    NB3M8T3910G

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    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The NB3M8T3910G is a 3:1:10 Clock fanout buffer operating on a 2.5 V/3.3 V Core VDD and a flexible 2.5 V / 3.3 V VDDO supply (VDDO ≤ VDD).A 3:1 Mux selects between Crystal oscillator inputs, or either of two differential Clock inputs capable of accepting LVPECL, LVDS, HCSL, or SSTL levels. The MUX select lines, SEL0 and SEL1, accept LVCMOS or LVTTL levels and select input per Table 3. The Crystal input is disabled when a Clock input is selected.Differential Outputs consist of two banks of five differential outputs with each bank independently mode configurable as LVPECL, LVDS, HCSL. Each bank of differential output pairs is configured with a pair of SMODEAx/Bx select lines using LVCMOS or LVTTL levels per Table 6. Clock input levels and outputs states are determined per Table 5.The Single?Ended LVCMOS Output, REFOUT, is synchronously enabled by the OE_SE control line per Table 4 using LVCMOS / LVTTL levels. For Clock frequencies above 250 MHz, the REFOUT line should be disabled.
    • Crystal, Single-Ended or Differential Input Reference Clocks
    • Differential Input Pair can Accept: LVPECL, LVDS, HCSL, SSTL
    • Two Output Banks: Each has Five Differential Outputs Configurable as LVPECL, LVDS, or HCSL by SMODEAx/Bx Pins
    • One Single?Ended LVCMOS Output with Synchronous OE Control
    • LVCMOS/LVTTL Interface Levels for all Control Inputs
    • Clock Frequency: Up to 1400 Mhz, Typical
    • Output Skew: 50 ps (Max)
    • Additive RMS Jitter
    • Input to Output Propagation Delay (900 ps Typical)
    • Operating Supply Modes VDD/VDDO: 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V
    • Industrial Temperature Range ?40°C to 85°C

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    型號制造商描述購買
    NB3M8T3910GMNR2GONNB3M8T3910G 是一款 3:1:10 時鐘扇出緩沖器，基于 2.5 V / 3.3 V 核心 VDD 和靈活的 3.3 V / 2.5 V VDDO 電源 (VDDO ≤ VDD) 運行。3:1 Mux 在晶體振蕩器輸入之間選擇，或者選擇兩個能夠接受 LVPECL、LVDS、HCSL 或 SSTL 電平的差分時鐘輸入之一。MUX 選擇線路 SEL0 和 SEL1 接受 LVCMOS 或 LVTTL電平，根據(jù)表 3 選擇輸入。 選擇時鐘輸入時，晶體輸入禁用。差分輸出由兩組輸出組成，每組五個差分輸出，每組均可獨立于模式配置為 LVPECL、LVDS、HCSL。每組差分輸出對均根據(jù)表 6 使用 LVCMOS 或 LVTTL 電平配置一對 MODEAx/Bx 選擇線路。 時鐘輸入電平和輸出狀態(tài)根據(jù)表 5 確定。 單端 LVCMOS 輸出 REFOUT 根據(jù)表 4，使用 LVCMOS / LVTTL 電平由 OE_SE 控制線路進行同步啟用。對于高于 250 MHz 的時鐘頻率，REFOUT 線路應禁用。 立即購買

    技術資料

    標題類型大小（KB）下載
    QFN48 7x7, 0.5PPDF35 點擊下載
    2.5 V /3.3 V 3:1:10 Configurable Differential Clock Fanout Buffer with LVCMOS Reference OutputPDF181 點擊下載
    NB3M8T3910G IBIS ModelUNKNOW190 點擊下載
    NB3M8T3910G Evaluation Board User"s ManualPDF1370 點擊下載

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