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    首頁(yè)產(chǎn)品索引NB100LVEP221

    NB100LVEP221

    購(gòu)買(mǎi)收藏
    20 Differential, HSTL / ECL / PECL, 2.5 V / 3.3 V

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The NB100LVEP221 is a low skew 2:1:20 differential driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential ECL/PECL; CLK1/CLK1bar can also receive HSTL signal levels. The LVPECL input signals can be either differential or single-ended (if the V
    output is used).
    The LVEP221 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from device to device.
    To ensure tightest skew, both sides of differential outputs should be terminated identically into 50 ohms even if only one output is being used. If an output pair is unused, both outputs may be left open (unterminated) without affecting skew.
    The NB100LVEP221, as with most other ECL devices, can be operated from a positive V
    supply in LVPECL mode. This allows the LVEP221 to be used for high performance clock distribution in +3.3 V or +2.5 V systems. In a PECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on PECL terminations, designers should refer to Application Note AND8020/D.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    Single-ended CLK input operation is limited to V
    >/= 3.0 V in LVPECL mode, or V
  • 15 ps Typical Output-to-Output Skew
  • 40 ps Typical Device-to-Device Skew
  • Jitter Less than 2 ps RMS
  • Maximum Frequency > 1.0 Ghz Typical
  • V
  • Output
  • 540 ps Typical Propagation Delay
  • LVPECL and HSTL Mode Operating Range: V
  • = 2.375 V to 3.8 V with V
  • = 0 V
  • NECL Mode Operating Range: V
  • = 0 V with V
  • = -2.375 V to -3.8 V
  • Q Output will Default Low with Inputs Open or at V

    • 電路圖、引腳圖和封裝圖

    在線購(gòu)買(mǎi)

    型號(hào)制造商描述購(gòu)買(mǎi)
    NB100LVEP221MNGONIC CLK BUFFER 2:20 1GHZ 52QFN 立即購(gòu)買(mǎi)
    NB100LVEP221MNRGONNB100LVEP221 是一款低歪曲率 2:1:20 差分驅(qū)動(dòng)器，適用于時(shí)鐘分發(fā)，將兩個(gè)時(shí)鐘源接受到一個(gè)輸入多路復(fù)用器中。兩個(gè)時(shí)鐘輸入為差分 ECL/PECL；CLK1/CLK1bar 還可接收 HSTL 信號(hào)電平。LVPECL 輸入信號(hào)可以為差分或單端（如果使用 VBB 輸出）。LVEP221 專(zhuān)門(mén)保證輸出對(duì)輸出的低歪曲率。絕佳的設(shè)計(jì)、布局和處理技術(shù)將器件內(nèi)部、器件到器件的歪曲率降到了最低。為了確保最嚴(yán)格的歪曲率，差分輸出的兩側(cè)均同樣端接到 50Ω，即使只使用一側(cè)也是如此。如不使用某個(gè)輸出對(duì)，可將兩個(gè)輸出保持開(kāi)路（無(wú)端接），而不影響歪曲率。與大多數(shù)其他 ECL 器件一樣，NB100LVEP221 可在 LVPECL 模式下由正向 VCC 電源供電。因此，在 +3.3 V 或 +2.5 V 系統(tǒng)中使用 LVEP221，可實(shí)現(xiàn)高性能的時(shí)鐘分發(fā)。在 PECL 環(huán)境中，通常使用串行或戴維南線路終端，因?yàn)樗鼈儫o(wú)需額外的電源。有關(guān)使用 PECL 端接的更多信息，設(shè)計(jì)人員應(yīng)參考應(yīng)用注釋 AND8020/D。僅為此器件提供 VBB 引腳，即內(nèi)部產(chǎn)生的供應(yīng)電壓。對(duì)于單端 LVPECL 輸入的情況，將未使用的差分輸入聯(lián)接至 VBB，作為開(kāi)關(guān)參考電壓。VBB 還可將 AC 耦合輸入重偏置。使用時(shí)，通過(guò)一個(gè) 0.01 uF 電容將 VBB 和 VCC 去耦合，并限制源或汲 0.5 mA 的電流。不使用時(shí)，VBB 應(yīng)保持開(kāi)路。單端 CLK 輸入運(yùn)行在 LVPECL 模式下僅限于 VCC >= 3.0 V，在 NECL 模式下僅限于 VEE <= -3.0 V。 立即購(gòu)買(mǎi)

    技術(shù)資料

    標(biāo)題類(lèi)型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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