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    首頁產品索引MC14042B

    MC14042B

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    ?Quad Transparent Latch

    制造商:ON

    中文數據手冊

    產品信息

    The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic "0" state, data is transferred during the low clock level, and when the polarity input is in the logic "1" state the transfer occurs during the high clock level.
    • Buffered Data Inputs
    • Common Clock
    • Clock Polarity Control
    • Q and Qbar Outputs
    • Double Diode Input Protection
    • Supply Voltage Range = 3.0 Vdc to 1 8 Vdc
    • Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
    • Pb-Free Packages are Available*

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    NLV14042BDGON 立即購買
    NLV14042BDR2GON 立即購買
    MC14042BDR2GON 立即購買
    MC14042BDGONMC14042B 四路透明鎖存在一個單片結構中使用 MOS P 溝道和 N 溝道增強模式器件構造。每個鎖存均具有單獨的數據輸入,但所有四個鎖存共享一個公共時鐘。用于通過鎖存頻閃數據的時鐘極性(高電平或低電平)可以使用極性輸入進行保留。數據輸入處呈現(xiàn)的信息在極性輸入確定的時鐘電平期間傳輸到輸出 Q 和 Q。當極性輸入為邏輯“0”狀態(tài)時,數據在時鐘低電平期間進行傳輸,當極性輸入為邏輯“1”狀態(tài)時,在時鐘高電平期間進行傳輸。 立即購買

    技術資料

    標題類型大?。↘B)下載
    Quad Transparent LatchPDF95 點擊下載
    IBIS Model for MC14042BCPUNKNOW5 點擊下載
    IBIS Model for MC14042BDUNKNOW5 點擊下載
    SOIC 16 LEADPDF37 點擊下載
    MC14042B_PKG.GIFUNKNOW13 點擊下載

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