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    首頁(yè)產(chǎn)品索引MC10E156

    MC10E156

    購(gòu)買收藏
    1 Mux-Latch

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10E/100E156 contains three 4:1 multiplexers followed by transparent latches with differential outputs. When both Latch Enables (LEN1, LEN2) are LOW, the latch is transparent, and output date is controlled by the multiplexer select controls (SEL0, SEL1). A logic HIGH on either LEN1 or LEN2 (or both) latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.
    The 100 Series contains temperature compensation.
    • 950ps Max. D to Output
    • 850ps Max. LEN to Output
    • Differential Outputs
    • Asynchronous Master Reset
    • Dual Latch-Enables
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • ESD Protection: > 2 kV HBM, > 200 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 271 devices
    • Pb-Free Packages are Available

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    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC10E156FNGONIC MULTIPLEXER 3 X 4:1 28PLCC 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大小（KB）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載

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