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    首頁產(chǎn)品索引MC10E151

    MC10E151

    購買收藏
    ?ECL 6-Bit D Register

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC10E/100E151 contains 6 D-type, edge-triggered, master-slave flip-flops with differential outputs. Data enters the master when both CLK1 and CLK2 are LOW, and is transferred to the slave when CLK1 or CLK2 (or both) go HIGH. The asynchronous Master Reset (MR) makes all Q outputs go LOW.
    The 100 Series contains temperature compensation.
    • 1100MHz Min. Toggle Frequency
    • Differential Outputs
    • Asynchronous Master Reset
    • DualClocks
    • PECL Mode Operating Range: V
    • = 4.2 V to 5.7 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -4.2 V to -5.7 V
    • Internal Input Pulldown Resistors
    • ESD Protection: > 2 kV HBM, > 200 V MM
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Moisture Sensitivity Level 1
    • For Additional Information, see Application Note AND8003/D
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 304 devices
    • Pb-Free Packages are Available

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    型號制造商描述購買
    MC10E151FNGONIC FF D-TYPE SNGL 6BIT 28PLCC 立即購買
    MC10E151FNR2GONIC FF D-TYPE SNGL 6BIT 28PLCC 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載

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