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    首頁產(chǎn)品索引MC100LVELT20

    MC100LVELT20

    購買收藏
    ?LVTTL/LVCMOS to Differential LVPECL Translator

    制造商:ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC?8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at a
    premium.
    The 100 Series contains temperature compensation.
    • 390 ps Typical Propagation Delay
    • Maximum Input Clock Frequency > 0.8 GHz Typical
    • Operating Range VCC = 3.0 V to 3.6 Vwith GND = 0 V
    • PNP TTL Input for Minimal Loading
    • Pb-Free Packages are Available

    電路圖、引腳圖和封裝圖

    在線購買

    型號(hào)制造商描述購買
    MC100LVELT20DR2GON 立即購買
    MC100LVELT20DGON 立即購買

    技術(shù)資料

    標(biāo)題類型大小(KB)下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載
    Interfacing with ECLinPSPDF72 點(diǎn)擊下載
    Termination of ECL Logic DevicesPDF176 點(diǎn)擊下載

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