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    首頁產(chǎn)品索引MC100LVEL92

    MC100LVEL92

    購買收藏
    ?Translator, Triple PECL Input to LVPECL Output

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVEL92 is a triple PECL input to LVPECL output translator. The device receives standard PECL signals and translates them to differential LVPECL output signals.
    To accomplish the PECL to LVPECL level translation, the MC100LVEL92 requires three power rails. The VCC supply is to be connected to the standard 5 V PECL supply, the LVCC supply is to be connected to the 3.3 V LVPECL supply, and Ground is connected to the system ground plane. Both the V
    and LVCC should be bypassed to ground with 0.01 F capacitors.
    The PECL V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    • 500ps Propagation Delays
    • 5V and 3.3V Supplies Required
    • ESD Protection: >2 KV HBM, >200 V MM
    • The 100 Series Contains Temperature Compensation
    • LVPECL Operating Range: LVCC = 3.0 V to 3.8 V
    • PECL Operating Range: V
    • = 4.5 V to 5.5 V
    • Internal Input Pulldown Resistors
    • Q Output will Default LOW with Inputs Open or
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 247 devices
    • Pb-Free Packages are Available

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    型號制造商描述購買
    MC100LVEL92DWR2GON 立即購買
    MC100LVEL92DWGON 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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