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    首頁產(chǎn)品索引MC100LVEL17

    MC100LVEL17

    購買收藏
    ?Quad Differential Receiver

    制造商：ON

    中文數(shù)據(jù)手冊

    產(chǎn)品信息

    The MC100LVEL17 is a 3.3 V ECL, quad differential receiver. The device is functionally equivalent to the E116 device with the capability of operation from either a -3.3 V or +3.3 V supply voltage.
    Under open input conditions, the Dbar input will be biased at V
    /2 and the D input will be pulled down to V
    . This operation will force the Q output LOW and ensure stability.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected toV
    as a switching reference voltage.V
    may also rebias AC coupled inputs. When used, decoupleV
    and V
    via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used,V
    should be left open.
    • 325 ps Propagation Delay
    • High Bandwidth Output Transitions
    • ESD Protection: >2 KV HBM
    • The 100 Series Contains Temperature Compensation
    • PECL Mode Operating Range: V
    • = 3.0 V to 3.8 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -3.8 V
    • Internal Input Pulldown Resistors
    • Q Output will Default LOW with Inputs Open or at V
    • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
    • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
    • Transistor Count = 141 devices

    電路圖、引腳圖和封裝圖

    在線購買

    型號制造商描述購買
    MC100LVEL17DWGONDifferential Receiver IC 20-SOIC 立即購買
    MC100LVEL17DWR2GONMC100LVEL17 是一款 3.3 V ECL，四路差分接收器。此器件功能相當(dāng)于器件 E116，可基于 -3.3 V 或 +3.3 V 電源運行。在開路輸入條件下，Dbar 輸入將在 VCC/2 處偏置，D 輸入將拉至 VEE。此操作將強制 Q 輸出進(jìn)入低電平，確保穩(wěn)定性。僅為此器件提供 VBB 引腳，即內(nèi)部產(chǎn)生的供應(yīng)電壓。對于單端輸入的情況，將未使用的差分輸入聯(lián)接至 VBB， 作為開關(guān)參考電壓。 VBB 還可將 AC 耦合輸入重偏置。使用時，通過 0.01 F 電容器對 VBB 和 VCC 進(jìn)行去耦合，并將源或汲電流限制為 0.5 mA。不使用時， VBB 應(yīng)保持開路。 立即購買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點擊下載
    ECL Clock Distribution TechniquesPDF54 點擊下載
    Interfacing Between LVDS and ECLPDF121 點擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點擊下載
    The ECL Translator GuidePDF142 點擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點擊下載

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