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    首頁產(chǎn)品索引MC100EP29

    MC100EP29

    購(gòu)買收藏
    ?ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

    制造商：ON

    中文數(shù)據(jù)手冊(cè)

    產(chǎn)品信息

    The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.
    The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to V
    and the Dbar input will bias around V
    /2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.
    Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.
    The V
    pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to V
    as a switching reference voltage. V
    may also rebias AC coupled inputs. When used, decouple V
    and V
    via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, V
    should be left open.
    The 100 Series Contains Temperature Compensation
    • Maximum Frequency > 3 GHz Typical
    • 500 ps Typical Propagation Delays
    • PECL Mode Operating Range: V
    • = 3.0 V to 5.5 V with V
    • = 0 V
    • NECL Mode Operating Range: V
    • = 0 V with V
    • = -3.0 V to -5.5 V
    • Open Input Default State
    • Safety Clamp on Inputs
    • These are Pb?Free Devices

    電路圖、引腳圖和封裝圖

    在線購(gòu)買

    型號(hào)制造商描述購(gòu)買
    MC100EP29MNGON 立即購(gòu)買
    MC100EP29MNTXGONIC FF D-TYPE DUAL 1BIT 20QFN 立即購(gòu)買
    MC100EP29DTR2GONMC10/100EP29 是一款雙路主從型觸發(fā)器。此器件提供全差分?jǐn)?shù)據(jù)和時(shí)鐘輸入及輸出。MC10/100EP29 與 MC10/100EL29 功能相同。當(dāng)時(shí)鐘為低電平時(shí)，數(shù)據(jù)進(jìn)入主鎖存，并在時(shí)鐘輸入正轉(zhuǎn)換時(shí)傳輸至從鎖存。差分輸入采用特殊電路，從而確保在開路輸入條件下的器件穩(wěn)定性。在兩個(gè)差分輸入保持開路條件下，Dbar 輸入將下拉至 VEE，并且 Dbar 輸入將偏向于 VCC / 2。輸出將進(jìn)入指定狀態(tài)，但根據(jù)觸發(fā)器的啟動(dòng)方式，狀態(tài)是隨機(jī)的。兩個(gè)觸發(fā)器都提供異步超控“設(shè)置”和“重置”輸入。請(qǐng)注意，設(shè)置和重置輸入不能同時(shí)為高電平。VBB 引腳（內(nèi)部產(chǎn)生的電源）僅可用于該器件。對(duì)于單端輸入情況，將未使用的差分輸入連接至 VBB，作為開關(guān)參考電壓。VBB 還可重新偏置交流耦合輸入。使用時(shí)，通過 0.01uF 電容器對(duì) VBB 和 VCC 進(jìn)行去耦合，并將源或汲電流限制為 0.5 mA。不使用時(shí)，VBB 應(yīng)保持開路。100 系列包含溫度補(bǔ)償。 立即購(gòu)買
    MC100EP29DTGON 立即購(gòu)買

    技術(shù)資料

    標(biāo)題類型大?。↘B）下載
    AC Characteristics of ECL DevicesPDF896 點(diǎn)擊下載
    ECL Clock Distribution TechniquesPDF54 點(diǎn)擊下載
    Interfacing Between LVDS and ECLPDF121 點(diǎn)擊下載
    Designing with PECL (ECL at +5.0 V)PDF102 點(diǎn)擊下載
    The ECL Translator GuidePDF142 點(diǎn)擊下載
    Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksPDF90 點(diǎn)擊下載
    ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuidePDF71 點(diǎn)擊下載
    Storage and Handling of Drypack Surface Mount DevicePDF49 點(diǎn)擊下載

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