優(yōu)勢和特點

  Supports Data Rates up to 32 Gbps

  660 mW Power Consumption

  -3.3 V or +3.3 V Operation

  Supports Single-Ended and Differential Operation

  24 Lead Ceramic 4 x 4 mm SMT Package: 16 mm2

  Invert Port Allows Scrambling for SERDES Application

產品詳情

The HMC955LC4B is a 1 to 2 Demux designed to support data transmission rates up to 32 Gbps. The demux uses both rising and falling edges of the half-rate clock to sample the data in sequence 01-02 and latches the data on the rising edge into the differential outputs. The demux also has high-speed clock synchronous invert input that allows for scrambling of the data. The HMC955LC4B also features an output level control pin, VR, which allows for loss compensation or for signallevel optimization.

All differential inputs to the HMC955LC4B are CML and terminated on-chip with 50 Ohms to the positive supply, GND, and may be AC or DC coupled. The differential CML outputs are source terminated to 50 Ohms and may also be AC or DC coupled. Outputs can be connected directly to a 50 Ohm ground-terminated system or drive devices with CML logic input. The HMC955LC4B operates from a single -3.3 V supply and is available in a ceramic ROHS-compliant 4 x 4 mm SMT package.

Applications

  SONET OC-192

  Broadband Test &?Measurement Equipment

  FPGA Interfacing Circuitry

  16 G and 32 G Fiber Channel

  100 Gbit Ethernet

  ADC Encoder